Samsung vyvíja 3 GB DDR5 čipy, umožnia 768 GB moduly
Diskusia k článku: Samsung vyvíja 3 GB DDR5 čipy, umožnia 768 GB moduly
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Re: Winnetou konica
Od: tvoja mama
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Pridané:
2021-07-31 14:30:08
Unlike DDR4, all DDR5 DIMMs will have in-chip ECC, where errors are detected and corrected before sending data to the CPU. There will still exist non-ECC and ECC DDR5 DIMM variants; the ECC variants will have extra data lines to the CPU to send error detection data, enabling the CPU to detect and correct errors that occurred in transit.
Each DIMM has two independent channels. While earlier SDRAM generations had one CA (Command/Address) bus controlling 64 or 72 (non-ECC/ECC) data lines, each DDR5 DIMM has two CA buses controlling 32 or 40 (non-ECC/ECC) data lines each, for a total of 64 or 80 data lines. This 4-byte bus width times a doubled minimum burst length of 16 preserves the minimum access size of 64 bytes, which matches the cache line size used by x86 microprocessors.
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